Recently a semiconductor device comprising a CMOS circuit including a PMOS transistor and an NMOS transistor is noted.
In such semiconductor device, for example, a gate interconnect is formed continuously in a PMOS transistor forming region and in a NMOS transistor forming region. A part of the gate interconnect in the PMOS transistor forming region functions as the gate electrode of the PMOS transistor, and a part of the gate interconnect in the NMOS transistor forming region functions as the gate electrode of the NMOS transistor.
On the semiconductor substrate with the PMOS transistor and the NMOS transistor formed on, an inter-layer insulation film is formed, covering the PMOS transistor and the NMOS transistor. In the inter-layer insulation film, a contact hole is formed down to the gate interconnect. In the contact hole, an electrically conductive plug is formed.
As a technique for increasing the carrier mobility of the PMOS transistor, an insulation film (compressive stress film) is used, covering the PMOS transistor so that compressive stresses are applied to a channel region of the PMOS transistor. As a technique for increasing the carrier mobility of the NMOS transistor, an insulation film (tensile stress film) is used, covering the NMOS transistor so that tensile stresses are applied to the channel region of the NMOS transistor.
Related reference is as follows:    Japanese Laid-open Patent Publication No. 2007-208166;    Japanese Laid-open Patent Publication No. 2008-16853;    Japanese Laid-open Patent Publication No. 2007-235074;    Japanese Laid-open Patent Publication No. 2008-124133; and    Japanese Laid-open Patent Publication No. 2009-206467.